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Frequency synthesizer for implementing generator of highly pure signals and circuit devices, such as VCO, PLL and SG, used therein
Frequency synthesizer for implementing generator of highly pure signals and circuit devices, such as VCO, PLL and SG, used therein
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机译:频率合成器,用于实现高纯信号发生器以及其中使用的电路设备,例如VCO,PLL和SG
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摘要
To output desired high purity signals, a frequency synthesizer was made to synthesize reference signals from a first and second signal generators (11, 12) in the same frequency band as a desired frequency band. Thereby, the resolution of the frequency synthesizer becomes twice the step ΔF. Also, the frequency synthesizer can interpolate the step size of the first signal generator with half the number of steps. While, heretofore, the 100-MHz step size was interpolated with Fq = 0, 10, 20, 30, 40 and 50 MHz, Fq = 0, 20, 40 MHz interpolation is made possible. This permits the synthesis of 580 MHz to 1280 MHz. In this case, however, the minimum difference between the sum and difference frequencies from the first and second signal generators (11, 12) is 40 MHz and the lowest frequency is 20 MHz. Thus, depending on mixer isolation, the spurious measures become difficult. The frequency synthesizer of the present invention pays attention to the fact that 20 MHz step signals can be synthesized at frequencies which are integral multiples of Fq (multiples of 0 and 5 are excluded). When two-fold Fq is used, the minimum difference between the sum and difference frequencies output from a mixer (13) is 80 MHz and the lowest used frequency is 40 MHz. The spurious measures by a PLL circuit (14) becomes easy. A frequency detector (18) forces the free-running frequency of a VCO included the PLL circuit. Control Data P and Q to the first and second signal generators are supplied from a control section (27) based on data Fi set by as frequency setting section (28).
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