首页> 外国专利> Frequency synthesizer for implementing generator of highly pure signals and circuit devices, such as VCO, PLL and SG, used therein

Frequency synthesizer for implementing generator of highly pure signals and circuit devices, such as VCO, PLL and SG, used therein

机译:频率合成器,用于实现高纯信号发生器以及其中使用的电路设备,例如VCO,PLL和SG

摘要

To output desired high purity signals, a frequency synthesizer was made to synthesize reference signals from a first and second signal generators (11, 12) in the same frequency band as a desired frequency band. Thereby, the resolution of the frequency synthesizer becomes twice the step ΔF. Also, the frequency synthe­sizer can interpolate the step size of the first signal generator with half the number of steps. While, heretofore, the 100-MHz step size was interpolated with Fq = 0, 10, 20, 30, 40 and 50 MHz, Fq = 0, 20, 40 MHz interpolation is made possible. This permits the syn­thesis of 580 MHz to 1280 MHz. In this case, however, the minimum difference between the sum and difference frequencies from the first and second signal generators (11, 12) is 40 MHz and the lowest frequency is 20 MHz. Thus, depending on mixer isolation, the spurious meas­ures become difficult. The frequency synthesizer of the present invention pays attention to the fact that 20 MHz step signals can be synthesized at frequencies which are integral multiples of Fq (multiples of 0 and 5 are excluded). When two-fold Fq is used, the minimum dif­ference between the sum and difference frequencies out­put from a mixer (13) is 80 MHz and the lowest used frequency is 40 MHz. The spurious measures by a PLL circuit (14) becomes easy. A frequency detector (18) forces the free-running frequency of a VCO included the PLL circuit. Control Data P and Q to the first and sec­ond signal generators are supplied from a control sec­tion (27) based on data Fi set by as frequency setting section (28).
机译:为了输出期望的高纯度信号,制造了频率合成器以在与期望的频带相同的频带中合成来自第一和第二信号发生器(11、12)的参考信号。由此,频率合成器的分辨率变为步长ΔF的两倍。而且,频率合成器可以用一半的步长内插第一信号发生器的步长。迄今为止,虽然以Fq = 0、10、20、30、40和50MHz对100MHz步长进行插值,但是使得Fq = 0、20、40MHz的内插成为可能。这允许合成580 MHz至1280 MHz。然而,在这种情况下,来自第一和第二信号发生器(11、12)的和与差频率之间的最小差为40MHz,而最低频率为20MHz。因此,取决于混频器的隔离度,杂散措施变得困难。本发明的频率合成器注意以下事实:可以在Fq的整数倍(不包括0和5的整数倍)的频率上合成20MHz的步进信号。当使用两倍Fq时,从混频器(13)输出的和频与差频之间的最小差为80MHz,而最低使用频率为40MHz。 PLL电路(14)的寄生措施变得容易。频率检测器(18)强制包含PLL电路的VCO的自由运行频率。基于由作为频率设置部分(28)设置的数据Fi,从控制部分(27)提供到第一和第二信号发生器的控制数据P和Q。

著录项

  • 公开/公告号EP0414260B1

    专利类型

  • 公开/公告日1997-05-28

    原文格式PDF

  • 申请/专利权人 ANRITSU CORP;

    申请/专利号EP19900116261

  • 申请日1990-08-24

  • 分类号H03B21/01;H03L7/087;H03L7/099;H03B19/16;

  • 国家 EP

  • 入库时间 2022-08-22 03:21:00

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号