Dynamic programmable logic array (PLA) in CMOS technology

摘要

The circuit includes an input register (RI) and an output register (RU); an AND plane formed by vertical lines (Y), which are controlled by the input register, and by horizontal lines (L) which include normally-off transistors (TA) which are arranged in series between the power supply and the ground and are controlled by respective vertical lines of the AND plane; an OR plane formed by horizontal lines (S), which are controlled by the horizontal lines of the AND plane, by vertical lines (U) between the power supply and the output register, and by normally-off transistors (TO) which can be connected between the ground and selected vertical lines and are controlled by respective horizontal lines of the OR plane. According to the invention, the connections toward the ground and toward the power supply of the horizontal lines of the AND plane are respectively constituted by normally-off transistors (TV) and by normally-on transistors (TP) which can be controlled by a first clock signal (CK1∼); the connections between the horizontal lines of the OR plane and, furthermore, the power supply are constituted by respective normally-on transistors (TR) which can be controlled by a second clock signal (CK2∼), and the connections between the horizontal lines of the AND plane and the horizontal lines of the OR plane are constituted by respective pairs of normally-on transistors (TB) and normally-off transistors (TC) arranged in series between the power supply and the ground. In each pair, the normally-on transistor is controlled by the horizontal line of the AND plane, the normally-off transistor is controlled by a third clock signal (CK2), and the horizontal line of the OR plane is connected to the node between the two transistors of the pair.