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A disparity detection circuit for a 2-bit to 4-bit coded signal decoder

机译:用于2位至4位编码信号解码器的视差检测电路

摘要

A disparity detection circuit used in a signal decoder which decodes a 4-bit signal into an original 2-bit main signal and 1-bit service signal, from which the 4-bit signal is coded according to a coding rule which stipulates that an original 2-bit main signal and 1-bit service signal should be coded into a 4-bit signal with 1 additional bit added and with pre-determined disparity carrying, determines whether the 4-bit signal conforms to the coding rule and detects the disparity of the 4-bit signal which is determined as conforming to the coding rule.
机译:在信号解码器中使用的视差检测电路,将视差检测电路将4位信号解码为原始的2位主信号和1位服务信号,并根据编码规则对4位信号进行编码,该编码规则规定了原始2位主信号和1位业务信号应编码为4位信号,并增加1位并带有预定的视差承载,确定4位信号是否符合编码规则并检测到视差。被确定为符合编码规则的4位信号。

著录项

  • 公开/公告号EP0514777B1

    专利类型

  • 公开/公告日1997-04-23

    原文格式PDF

  • 申请/专利权人 FUJITSU LTD;

    申请/专利号EP19920108181

  • 申请日1992-05-14

  • 分类号H04L25/49;

  • 国家 EP

  • 入库时间 2022-08-22 03:20:52

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