PLL frequency synthesizer and PLL frequency synthesizing method capable of obtaining high-speed lock-up and highly-reliable oscillation

摘要

According to an output from a voltage-controlled oscillator (1), there are generated by a fractional divider (2) a high-frequency division signal (S1) and a low-frequency division number (S2). A phase comparison is conducted betwen the high-frequency division signal (S1) and a high-frequency reference signal (REF1) by a phase comparator (5). A phase comparison is carried out between the low-frequency division signal (S2) and a low-frequency reference signal (REF2) by a phase comparator (6). Either one of the outputs from the phase comparators (5 and 6) is selected by a selector (7) to be fed to a filter (8), thereby producing a control voltage (Vc) for the voltage-controlled oscillator (1). A high-resolution division is achieved by the fractional division; consequently, disturbance of the oscillation frequency due to a change-over of the selector (7) is suppressed. There is obtained a PLL frequency synthesizer developing a high-speed lock-up and a highly stable oscillation. IMAGE