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STICKY bit generator circuit of multiplier

机译:乘法器的STICKY位发生器电路

摘要

According to an embodiment of the present invention, a plurality of sticker generators which are exclusively logically coupled with a carry vector and a sum vector output from a plurality of carry adders and are connected and propagated dependently and a logical sum of data output from the plurality of stickers The present invention relates to a STICKY bit generating circuit of a multiplier, which is composed of a combination unit for generating a sticky bit, so that multiplication is performed by generating rounded bits in real time to speed up rounding.;Selectivity: first degree
机译:根据本发明的实施例,多个标签产生器被排他地逻辑地耦合从进位向量和从多个进位加法器输出的和向量,并且被独立地连接和传播,并且从这多个输出产生逻辑和。贴纸的制作方法本发明涉及一种乘法器的STICKY位生成电路,该电路由用于生成粘性位的组合单元组成,从而通过实时生成舍入的位以加快舍入来进行乘法。度

著录项

  • 公开/公告号KR970012121A

    专利类型

  • 公开/公告日1997-03-29

    原文格式PDF

  • 申请/专利权人 김광호;

    申请/专利号KR19950027271

  • 发明设计人 천성훈;

    申请日1995-08-29

  • 分类号G06F7/38;

  • 国家 KR

  • 入库时间 2022-08-22 03:18:04

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