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An information handling system, including uninterrupted movement of instructions and data between a storage device and one or more coprocessors
An information handling system, including uninterrupted movement of instructions and data between a storage device and one or more coprocessors
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机译:一种信息处理系统,包括在存储设备和一个或多个协处理器之间不间断地移动指令和数据
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摘要
An information handling system that effectively handles auxiliary functions such as graphics processing may include one or more processors, a high-speed processor bus connecting one or more processors, a memory controller that controls memory and controls auxiliary function processing, a memory system, and And an I / O bus having one or more controllers to which the I / O devices are connected. The system also creates a queue of command blocks associated with the assistive function processor, writes one or more instruction blocks to a memory that may include a processor cache, and provides a start address assistance function for each instruction block Writes to the address FIFO associated with the processor, reads the instruction block queue start address by the coprocessor, recognizes the instruction block read, enables intervention and issues a synchronous read instruction to the queued instruction blocks flushes a copy of the queued instruction block from the processor cache to the memory subsystem when a copy of the queued block is in the processor cache, Intercepts a copy of the queued command block flushed to RTI ID = 0.0 Canceling the above read into memory, storing the queued block in the instruction buffer associated with the auxiliary function processor, processing the instruction in the queue by the auxiliary function processor and returning the completion status to the processor upon completion of the auxiliary function processing In a processor at a predetermined location that is periodically polled by the processor. For each data request from or to the storage device from the auxiliary function processor, it is determined whether there is a request for coherent or non-coherent reading or writing of the data. If the request is an asynchronous read or write, a snoop cycle on the processor bus is prohibited and bypassed because there is no need to snoop to maintain coherency for asynchronous data . This data request is then handled and processed.
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