A random number generator having an atmospheric control circuit for improving the randomness of the number read from the random number generator

摘要

Disclosed herein is a random number generator circuit that generates a series of random numbers. The linear feedback shift register includes a shift register circuit for holding a plurality of shift register bits. Wherein the shift register circuit shifts the shift register bit in response to a periodic system clock signal, shifting one of the shift register bits out and shifting a feedback bit having a value provided to the feedback input of the shift register inward, . The tap circuit generates the feedback bits by logically combining selected shift register bits of the shift register bits. The sampling circuit provides at least a portion of the shift register bits as one of the series of random waters. The interface circuit provides a random number from the shift register to the processor via the processor bus in response to the asserted processor request signal.;Importantly, the interface circuit receives the asserted processor request signal and, when the asserted processor request signal occurs less than a minimum number of cycles of the system clock signal from the asserted processor request signal, And a standby control circuit for inserting a standby state into the standby state. Preferably, the " minimum number of cycles " is determined from registers that can be programmed by the processor. Thus, the randomness of the order generated by the linear feedback shift register improves in situations where the processor requires a random number that is time-to-density.