Lock guarantee and cache consistency guarantee for data during lock operation in multiprocessor system

摘要

The present invention relates to a lock guarantee and a cache consistency guarantee device in a multiprocessor system. The present invention relates to a lock guarantee and cache consistency guarantee device in a multiprocessor system. First to second latch means for storing and outputting a lock address from a bus, and a first latch indicating whether or not the output value of the first latch means and the lock address value currently being executed on the bus are compared and equal. A first latch comparison means for outputting a matching signal; a second latch matching signal indicating whether or not the output value of the second latch means and the lock address value currently being executed on the bus are compared and equally output; A source expression that is an identifier of the latch comparison means and the processor module that requested the ongoing cycle on the bus Identifier comparison means for comparing an asterisk with its own unique identifier and outputting an identifier matching signal indicating whether it is the same or not, and checking whether or not the type of the cycle in progress on the bus is a lock-related type. Transmission mode comparing means for outputting an interlock read signal indicating a transmission type cache signal and a lock read related cycle and an interlock write signal indicating a lock write related cycle, the identifier matching signal, the interlock read signal, and the inter A memory response signal indicating the lock write signal and the memory module state, a processor snoop non-response signal indicating the success of the snooping by indicating the state of the processor module, and a bus enable signal indicating that a cycle in progress on the bus has been successfully completed; Bus award Control means for receiving a stop signal and the bus clock indicating that the process is not completed successfully and canceling the cycle, and outputting a first request signal and a second request signal, and receiving the first request signal and the bus clock A first lock notification means for outputting a first lock progress signal indicating that a lock-related cycle is in progress, and a second lock progress signal for receiving a second request signal and the bus clock and outputting a second lock progress signal indicating that a lock-related cycle is currently in progress; A processor snoopy ratio for receiving a second lock notification means, the first lock progress signal, the second lock progress signal, the first latch match signal, the second latch match signal, and the transfer type cache signal to prohibit snooping; Since it includes a processor snoop non-response signal generating means for outputting a response signal, the effect is that the state transition diagram The logic circuit is very simple by using the logic circuit.