首页> 外国专利> Vector processing unit that accepts cosine transform / inverse cosine transform / quantization / inverse quantization operation

Vector processing unit that accepts cosine transform / inverse cosine transform / quantization / inverse quantization operation

机译:接受余弦变换/逆余弦变换/量化/逆量化运算的矢量处理单元

摘要

The present invention relates to a vector processing apparatus that accepts a cosine transform / inverse cosine transform / quantization / inverse quantization operation. The present invention relates to a DCT preprocess for performing preprocessing according to a cosine transform / inverse cosine transform / quantization / inverse quantization operation. Means (10); Data storage means 20 for storing a value of 1 / QP and outputting the index value by an index value to avoid division during DCT / IDCT coefficient and quantization (Q); Multiplication operation means (30) which receives the output of the DCT preprocessing means (10) and the output of the data storage means (20) and multiplies it in two steps; In the DCT / IDCT operation, the output of the multiplication operation means 30 performed four times is accumulated and output, and in the Q operation, '0' is added to the output value of the multiplication operation means 30 and output. Accumulating means (40) for adding the value of the quantization parameter (QP) or QP-1 to the output value of the multiplication calculating means (30) during the calculation; And an IDCT post-processing means 50 for storing only four accumulated values of the accumulation means 40 at the time of IDCT operation, discarding the rest, storing two values, performing an addition operation, and outputting an IDCT value. When the unit operation of DCT / IDCT / Q / IQ is controlled according to the calculation type, the hardware can be efficiently shared, thereby reducing the complexity of the hardware.
机译:矢量处理设备技术领域本发明涉及一种接受余弦变换/逆余弦变换/量化/逆量化操作的矢量处理装置。 DCT预处理技术领域本发明涉及一种DCT预处理,用于根据余弦变换/逆余弦变换/量化/逆量化操作进行预处理。均值(10);数据存储装置20,用于存储1 / QP的值并通过索引值输出索引值,以避免在DCT / IDCT系数和量化(Q)期间进行除法;乘法运算装置(30),其接收DCT预处理装置(10)的输出和数据存储装置(20)的输出,并将其分两步相乘;在DCT / IDCT运算中,四次执行的乘法运算装置30的输出被累积并输出,并且在Q运算中,将“ 0”加到乘法运算装置30的输出值并输出。累加装置(40),用于在计算期间将量化参数(QP)或QP-1的值加到乘法计算装置(30)的输出值上;并且,IDCT后处理装置50用于在IDCT操作时仅存储累加装置40的四个累加值,丢弃其余的,存储两个值,执行加法运算,并输出IDCT值。当根据计算类型控制DCT / IDCT / Q / IQ的单元操作时,可以有效共享硬件,从而降低了硬件的复杂性。

著录项

  • 公开/公告号KR970057942A

    专利类型

  • 公开/公告日1997-07-31

    原文格式PDF

  • 申请/专利权人 이준;

    申请/专利号KR19950066689

  • 发明设计人 김정민;채수익;전기호;전준현;

    申请日1995-12-29

  • 分类号H04N7/28;

  • 国家 KR

  • 入库时间 2022-08-22 03:16:28

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