首页> 外国专利> A method for calculating an average of four integers rounded from zero in a single instruction cycle and computing the average of the four integer numbers rounded away from a single instruction cycle.

A method for calculating an average of four integers rounded from zero in a single instruction cycle and computing the average of the four integer numbers rounded away from a single instruction cycle.

机译:一种用于在单个指令周期中计算从零取整的四个整数的平均值,并计算从单个指令周期取整的四个整数的平均值的方法。

摘要

The present invention relates to an average calculation method for four integer arithmetic operations and an apparatus therefor, wherein four encoded or non-encoded n-bit integer arithmetic operations (A, B, C, D ) Provides four n + 2 bit extended operation numbers by adding two bits to the left of each operation number to provide an n + 2 bit sum by summing the extended operation numbers, and the n + Is calculated in a single instruction cycle by removing the two least significant bits of the 2-bit sum to provide an n-bit sum and appropriately increasing its n-bit sum. The adder circuit 302 adds 2 bits to the left of the number of operations and the expansion number is coupled to an adder circuit including an adder logic 308 and an n-bit carry lookhead adder 310. [ The adder logic 308 provides the adder 310 with two least significant bits of the sum of the number of extended operations with a partial sum of n bits and a partial carry of n bits. The adder 310 provides a sum output representing the most significant bit of the sum n of the number of extended operations and a sum + 1 output representing the sum output increased by one. Multiplexer 9314) receives the sum of the sum and the sum of the summation of the two least significant bits and the most significant bit of the sum of the number of extended operations and the sum 1 output as an n-bit average.
机译:本发明涉及一种用于四个整数算术运算的平均计算方法及其装置,其中四个编码或非编码的n位整数算术运算(A,B,C,D)提供四个n + 2位扩展运算数通过在每个运算号的左边加两位来通过对扩展的运算号求和来提供n + 2位和,并且在单个指令周期中通过去除2位和的两个最低有效位来计算n +提供一个n位和,并适当增加其n位和。加法器电路302在操作数的左边加2位,并且扩展数耦合到包括加法器逻辑308和n位进位看头加法器310的加法器电路。[加法器逻辑308向加法器310提供扩展操作数之和的两个最低有效位,其中n位的部分和与n位的部分进位。加法器310提供代表扩展操作的数目的总和n的最高有效位的总和输出和代表增加了1的总和输出的总和+1输出。多路复用器9314)接收扩展运算的数目与和1的和的总和,两个最低有效位的和与最高有效位的和之和作为n位平均值输出。

著录项

  • 公开/公告号KR970073163A

    专利类型

  • 公开/公告日1997-11-07

    原文格式PDF

  • 申请/专利权人 윤종용;

    申请/专利号KR19970012517

  • 发明设计人 로니 에스 웡;

    申请日1997-04-04

  • 分类号H04N7/32;

  • 国家 KR

  • 入库时间 2022-08-22 03:16:12

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