Low-voltage BiCMOS digital delay chain suitable for operation over a wide power supply range

摘要

The BiCMOS digital delay chain has two signal paths coupled between the input terminal and the output terminal. The first signal path has two CMOS inverters coupled in series, while the second passage has one CMOS inverter coupled to the BiCMOS inverter, which is coupled to the BiCMOS pull-down circuit. By providing two signal paths between the input and output terminals of the delay chain, a zero constant power low voltage circuit can achieve higher power sensitivity in either of the two switching directions. These characteristics allow operation over a wide range of potentials while minimizing variations in direct circuit performance.