Self-Align Source Process for High Density Memory (PROCESS FOR SELF-ALIGNED SOURCE FOR HIGH DENSITY MEMORY)

摘要

An improved method of protecting a gate edge adjacent a source region of a semiconductor device is described. In this way, the spacers are formed along the gate of a transistor of the type to protect the gate edge and the adjacent source region during the self-aligned source etch. Spacers of different widths that can be optimized for different voltage requirements are formed along the gates of the second type transistors of the same integrated circuit. This method is particularly applicable to the formation of an EPROM, a flash EPROM, an EPROM or other memory cell in connection with peripheral devices required to maintain a relatively high voltage. By decoupling memory cell requirements from peripheral device requirements, tighter gate spacing and smaller cell size can be achieved.