PROCESSOR FOR RAPID Hartley Transform

摘要

A processor for Fast Hartley transform, comprising a memory unit, a volatile memory, a counter, an OR gate, the switch address, the control unit, the output of the switch address is connected with the address inputs of the group of the storage unit, the input of which write enable is coupled to the first output of the control unit, the input of which connected to the counter output, a second output of the control unit is connected to the control input of switch addresses, characterized in that the driver has entered three addresses, three aND gates and an arithmetic unit, wherein bus input data processor coupled to the data inputs of the first, second and third generators addresses, address outputs of the first and second formers addresses connected to the first and second information inputs of switch addresses, respectively, the output of which is an address output of the processor, the input clock frequency of which is connected to the first inputs of the first , second and third aND gates, respectively, the first output of the first address generator is connected to the first input of the OR gate, the second output of the first form of rovatelya addresses is coupled to the second input of the second AND gate, whose output is connected to a clock input of the arithmetic unit and a counting input of the counter, setting the input to zero which is connected to the output of the OR gate, the output of the third driver addresses connected to the input-volatile memory block, the outputs of the storage unit and permanent memory unit are connected to first and second data inputs respectively of the arithmetic unit, a third and fourth outputs of the control unit are connected to second inputs of the third and first element and soot respectively, an output of first AND gate is connected to the control inputs of the first and third generators address output of the third AND gate is connected to the control input of the said second address storage unit output connected to the output of the arithmetic unit, and an information processor output, the fifth control unit output connected to the input feature , the memory unit, the sixth and seventh outputs of the control unit area are connected to the first and second write enable inputs of the arithmetic unit, output the eighth control unit is connected to input of feature operation of the arithmetic unit code, the ninth control unit is connected to the output of the arithmetic unit control input, write enable input of the third of which is connected to a tenth output control unit, eleventh output is connected to a second input of the OR element.