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The data processing system with direct memory access control and process for the bus master change using gaps with a given priority
The data processing system with direct memory access control and process for the bus master change using gaps with a given priority
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机译:具有直接内存访问控制和总线主控程序处理能力的数据处理系统使用给定优先级的间隙进行更改
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摘要
A data processing system having a direct memory access controller (DMAC) which can be interrupted with a prioritized signal to vary bus mastership of a communication bus in the system. A prioritized interrupt signal is sent to a CPU when the DMAC has bus mastership. The CPU only informs the DMAC of the highest priority cumulative interrupt priority. With the use of a mask value, the interrupt may be selectively screened by the DMAC so that selective interrupts may remove bus mastership from the DMAC.
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