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Examination of design rules with a VHDL simulator
Examination of design rules with a VHDL simulator
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机译:用VHDL模拟器检查设计规则
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摘要
We describe the application of VHDL simulators to check the conformance of a design with Design for Testability (DFT) rules. The basic idea is to define a special DFT logic using VHDL's powerful logic modeling capabilities and to perform a kind of symbolic simulation based on this DFT logic.
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