Modular arithmetic co-processor for non-modular operations e.g. Galois field for cryptography

摘要

The arithmetic co-processor has a multiplexer formed of two individual multiplexers (40,41). The first multiplexer has an input receiving a permanent logic state, and its other input connected to the output of a subtractor circuit (28). The output is connected to a first adder circuit (30). The second multiplexer (41) has an input connected to the output of this adder circuit and an output connected to a register (11). The register output is connected to a third input of the first multiplexer (40). The adder circuit has its input connected to a multiplier (19), whose output is added to the output of the register.