Branch history with inhibit bits

摘要

In an information processing apparatus, an instruction read inhibit bit GIDDY is provided for each pair of addresses comprising a branch instruction address IA and target instruction address TIA registered in the branch history 1. When the reading of a target instruction predicted from the pair of addresses IA and TIA is inhibited, the instruction read inhibit bit GIDDY is set to an ON state. When execution of the predicted target instruction is canceled due to the difference between the predicted target instruction and an actual target instruction and the actual target instruction is read again, an instruction read inhibit bit setting section 2 sets the instruction read inhibit bit GIDDY of the pair of addresses IA and TIA in the branch history 1 to the ON state.