Providing a forced miss signal for a cache tag memory concurrent with outcome of address comparison

摘要

Comparator 18 compares an address A from a tag RAM with an address B to which the processor requires access to determine if address B is cached. The comparator enables transistor 20 when the addresses do not match thus setting the hit signal HIT1 to ground. The miss forcing circuit 14 connects line HITG, which is grounded, to HIT1 through itself if a miss is to be forced. The address comparator 18 operates when the address A arrives and to synchronise the output from the miss forcing circuit 14 with that of the address comparator 18 the connection of HIT1 to grounded HITG in the miss forcing circuit 14 comprises transistors controlled by the arrival of bits from the address A supplied by the tag RAM.