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Cache memory system having first and second direct-mapped cache memories organized in hierarchical structure

机译:具有以分层结构组织的第一和第二直接映射高速缓冲存储器的高速缓冲存储器系统

摘要

A microprocessor includes a CPU, a main memory and primary and second cache memories of the direct mapped type, that are all implemented on the same LSI chip. The second cache memory's capacity is not greater than the primary cache memory. The primary and second cache memories are organized in a hierarchical structure so that the primary cache memory is accessed before the secondary cache memory, and when the first cache memory is not hit, the secondary cache memory is accessed. Thus, a high performance microprocessor having a small chip area is constructed by adding a small, high speed secondary cache memory, rather than by increasing the memory capacity of the primary cache memory.
机译:微处理器包括CPU,主存储器以及直接映射类型的主高速缓存和第二高速缓存,它们均在同一LSI芯片上实现。第二个缓存的容量不大于主缓存的容量。主高速缓冲存储器和第二高速缓冲存储器以分层结构组织,从而在二级高速缓冲存储器之前访问初级高速缓冲存储器,并且当未命中第一高速缓冲存储器时,二级高速缓冲存储器被访问。因此,通过增加小的高速辅助二级高速缓冲存储器,而不是通过增加一级高速缓冲存储器的存储容量,来构造具有小芯片面积的高性能微处理器。

著录项

  • 公开/公告号US5581725A

    专利类型

  • 公开/公告日1996-12-03

    原文格式PDF

  • 申请/专利权人 NEC CORPORATION;

    申请/专利号US19930129409

  • 发明设计人 TAKASHI NAKAYAMA;

    申请日1993-09-30

  • 分类号G06F12/08;G06F13/00;

  • 国家 US

  • 入库时间 2022-08-22 03:11:00

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