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Compiling apparatus having a function to analyze overlaps of memory addresses of two or more data expressions and a compiling method

机译:具有分析两个或更多个数据表达式的存储器地址的重叠的功能的编译装置和编译方法

摘要

An object of the present invention is to realize a compiling apparatus producing an object program which can be executed at a high speed. In a compiling apparatus according to the present invention, an aliasing address comparison instruction generating unit inserts a instruction to compare the two memory addresses of each pair of data expressions whose overlap is judged to be obscure, generates a plurality of paths defined by combinations of conditions whether or not memory addresses of data expressions of each pair overlap, and generates a instruction to branch to one of the paths according to a comparison result obtained by the instruction in an execution of a compiled program, and an optimization unit for respectively optimizing the paths. When the object program is executed, one path corresponding to a practical condition is selected from the plurality of paths, and only the selected path is executed.
机译:本发明的目的是实现一种编译设备,该编译设备产生可以高速执行的目标程序。在根据本发明的编译设备中,别名地址比较指令生成单元插入指令以比较被判断为重叠的每对数据表达式的两个存储地址,并生成由条件组合定义的多个路径。每对数据表达式的存储地址是否重叠,并根据指令在编译程序的执行中获得的比较结果生成分支到路径之一的指令,以及用于分别优化路径的优化单元。当执行目标程序时,从多个路径中选择与实际条件相对应的一个路径,并且仅执行所选择的路径。

著录项

  • 公开/公告号US5581762A

    专利类型

  • 公开/公告日1996-12-03

    原文格式PDF

  • 申请/专利权人 FUJITSU LIMITED;

    申请/专利号US19940202580

  • 发明设计人 TADASHI NAKAHIRA;MASAKAZU HAYASHI;

    申请日1994-02-28

  • 分类号G06F9/44;

  • 国家 US

  • 入库时间 2022-08-22 03:11:00

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