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Compiling apparatus having a function to analyze overlaps of memory addresses of two or more data expressions and a compiling method
Compiling apparatus having a function to analyze overlaps of memory addresses of two or more data expressions and a compiling method
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机译:具有分析两个或更多个数据表达式的存储器地址的重叠的功能的编译装置和编译方法
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摘要
An object of the present invention is to realize a compiling apparatus producing an object program which can be executed at a high speed. In a compiling apparatus according to the present invention, an aliasing address comparison instruction generating unit inserts a instruction to compare the two memory addresses of each pair of data expressions whose overlap is judged to be obscure, generates a plurality of paths defined by combinations of conditions whether or not memory addresses of data expressions of each pair overlap, and generates a instruction to branch to one of the paths according to a comparison result obtained by the instruction in an execution of a compiled program, and an optimization unit for respectively optimizing the paths. When the object program is executed, one path corresponding to a practical condition is selected from the plurality of paths, and only the selected path is executed.
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