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Semiconductor integrated circuit device with test mode for testing CPU using external Signal

机译:具有测试模式的半导体集成电路器件,用于使用外部信号测试CPU

摘要

An output gate means is provided which is capable of outputting individual signals selectively to an internal bus; the individual signals are interchanged among a plurality of functional modules connected to the internal bus which is interfaced with an external circuit. An input gate means is provided which is capable of supplying selectively a signal, input to the internal bus, to a specified functional module in place of an individual signal.
机译:提供了一个输出门装置,它能够有选择地将各个信号输出到内部总线。各个信号在连接到内部总线的多个功能模块之间交换,该内部总线与外部电路接口。提供了一种输入门装置,该输入门装置能够选择性地将输入到内部总线的信号提供给指定的功​​能模块,以代替单个信号。

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