首页> 外国专利> Bus-to-bus read prefetch logic for improving information transfers in a multi-bus information handling system (bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus)

Bus-to-bus read prefetch logic for improving information transfers in a multi-bus information handling system (bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus)

机译:总线到总线读取预取逻辑,用于改善多总线信息处理系统中的信息传输(用于多总线信息处理系统的总线到总线桥,可优化系统总线和外围总线之间的数据传输)

摘要

A method and system for improving bus-to-bus data transfers in a multi- bus computer system is provided. The system includes a system bus having a slave device attached thereto, a peripheral bus having a master device attached thereto, and a host bridge connecting the two buses. The system bus permits burst read transfers of data stored in the slave device, wherein a single address phase is followed by several data phases, but only if the first address corresponds to a prescribed system bus boundary. The peripheral bus is not subject to address boundary limitations, instead permitting burst read transfers beginning at any address. The host bridge includes logic for decoding a first address asserted by the master device to determine if it corresponds to a system bus boundary. If it does not, the logic commences a first read pre-fetch non-burst transfer of a first set of data stored in the slave device beginning at the first address and ending at a system bus boundary, and temporarily stores this first set of data in a buffer. The logic then commences a second read pre-fetch burst transfer of a second set of data stored in the slave device corresponding to data stored between system bus boundaries, and temporarily stores this second set of data in the buffer, so that both of the temporarily stored first and second sets of data may be read by the master device over the peripheral bus in a single burst read transfer.
机译:提供了一种用于改善多总线计算机系统中的总线到总线数据传输的方法和系统。该系统包括具有附接到其上的从设备的系统总线,具有附接到其上的主设备的外围总线以及连接这两个总线的主机桥。系统总线允许突发读取传输存储在从设备中的数据,其中只有一个地址阶段之后是几个数据阶段,但前提是第一地址对应于规定的系统总线边界。外设总线不受地址边界的限制,而是允许从任何地址开始的突发读取传输。主机桥包括用于解码由主设备断言的第一地址以确定其是否对应于系统总线边界的逻辑。如果不是,则逻辑开始对存储在从设备中的第一组数据的第一读取预取非突发传输,该第一组数据从第一地址开始并在系统总线边界处结束,并临时存储此第一组数据在缓冲区中。然后,该逻辑开始对与系统总线边界之间存储的数据相对应的从设备中存储的第二组数据进行第二次读取预取突发传输,并将该第二组数据临时存储在缓冲区中,以便主设备可以在单个突发读取传输中通过外围总线读取存储的第一和第二组数据。

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