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Process and apparatus for etching metal in integrated circuit structure with high selectivity to photoresist and good metal etch residue removal

机译:具有高的光刻胶选择性和良好的金属蚀刻残留物去除能力的集成电路结构中的金属蚀刻工艺和装置

摘要

A process and apparatus are described for patterning a masked metal layer to form a layer of metal interconnects for an integrated circuits structure which removes metal etch residues, while inhibiting or eliminating erosion of the photoresist mask, by providing an amplitude modulation of the RF bias power supplied to the substrate support of the substrate being etched. The amplitude modulation of the RF power superimposes short pulses of RF power of sufficient magnitude (pulse height) and of sufficient duration (pulse width) to remove metal etch residues as they form during the etch process without, however, eroding the photoresist etch mask during the etch process sufficiently to adversely impact the patterning of the metal layer.
机译:描述了一种用于对掩模的金属层进行构图以形成用于集成电路结构的金属互连层的方法和装置,该集成电路结构通过提供RF偏置功率的幅度调制来去除金属蚀刻残留物,同时抑制或消除光刻胶掩模的腐蚀。供给被蚀刻衬底的衬底支撑。 RF功率的幅度调制会叠加足够大小(脉冲高度)和足够持续时间(脉冲宽度)的RF功率短脉冲,以去除在蚀刻过程中形成的金属蚀刻残留物,但是不会在蚀刻过程中腐蚀光刻胶蚀刻掩模蚀刻工艺足以不利地影响金属层的图案。

著录项

  • 公开/公告号US5614060A

    专利类型

  • 公开/公告日1997-03-25

    原文格式PDF

  • 申请/专利权人 APPLIED MATERIALS INC.;

    申请/专利号US19950409388

  • 发明设计人 HIROJI HANAWA;

    申请日1995-03-23

  • 分类号H01L21/00;H05H1/00;

  • 国家 US

  • 入库时间 2022-08-22 03:10:25

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