Method and apparatus for fast synchronization of T1 extended superframes

摘要

A T1 digital PCM signal frame synchronizer includes a RAM memory for storing a complete extended superframe of received data, a pattern detector for detecting patterns in the memory that match a predetermined frame alignment signal, and a plurality of address pointer registers and associated counters. A given address within the RAM corresponds to a particular bit position within the received data. The first time that a pattern is detected at a given address within memory, that address is stored into a register, and its associated counter set to one. Subsequent pattern matches and violations at that address cause the counter to increment and decrement, respectively. A register whose counter value decrements down to zero becomes available for storing a new address. In- sync is declared when any counter exceeds an in-sync threshold. Out-of- sync is declared when that counter falls to an out-of- sync threshold or below. The synchronizer continues to search for alternative candidates even after synchronization is declared. When the number of registers provided is limited, initial synchronization speed is increased by storing the address for only every other pattern match for the first three extended superframes of received data, thus ensuring that the pattern matches initially recorded will be more evenly distributed throughout the extended superframe of received data.