首页> 外国专利> Method and apparatus for serial bus elements of an hierarchical serial bus assembly to electrically represent data and control states to each other

Method and apparatus for serial bus elements of an hierarchical serial bus assembly to electrically represent data and control states to each other

机译:用于分层串行总线组件的串行总线元件相互电表示数据和控制状态的方法和装置

摘要

Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical bus assembly for electrically representing data and control states each other. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. The serial bus elements are interconnected to each other using low cost two wire signal cable. Electrical signals are propagated between the serial bus elements in a differential manner. These circuitry and complementary logic of the serial bus elements jointly implement inference of data and control states from the states and/or durations of the propagating electrical signals.
机译:电路和互补逻辑被提供给总线控制器,多个1:n总线信号分配器以及分层总线组件的多个总线接口,用于相互电表示数据和控制状态。分层串行总线组件用于将许多同步和异步外围设备串行接口到计算机系统的系统单元。串行总线元件使用低成本的两线信号电缆相互互连。电信号以差分方式在串行总线元件之间传播。串行总线元件的这些电路和互补逻辑共同实现从传播的电信号的状态和/或持续时间推断数据和控制状态。

著录项

  • 公开/公告号US5621901A

    专利类型

  • 公开/公告日1997-04-15

    原文格式PDF

  • 申请/专利权人 INTEL CORPORATION;

    申请/专利号US19940332337

  • 发明设计人 JEFF C. MORRISS;ANDREW M. VOLK;

    申请日1994-10-31

  • 分类号G06F13/40;

  • 国家 US

  • 入库时间 2022-08-22 03:10:15

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