Method and apparatus for verifying a target instruction before execution of the target instruction using a test operation instruction which identifies the target instruction

摘要

A Test Operation-Code (TSTOP) instruction pre-verifies the validity of a target instruction op-code prior to execution of the target instruction. The pre-verification function, contained within CPU execution unit microcode, sets a return value in a program status word to indicate one of four conditions:PP1. The target instruction is present and operable;PP2. The target instruction is present in the computer system, but unavailable on this central processor (e.g. an asymmetric feature).PP3. The target instruction is not present in this computer system.P P4. The TSTOP op-code is recognized, but the target instruction presence cannot be determined. PPThe return value is testable by the program issuing the TSTOP instruction to determine whether the target instruction should be issued.