Integrated content addressable memory array with processing logical and a host computer interface

摘要

An associative processing memory system for concurrent data searching or processing includes a content addressable memory (CAM) array, a general register block, an interface register logic block, and a general control block. The CAM array is accessed for read or write by a select vector generated by the general register logic block. The select vector is selected through a multiplexer from at least four sources: the match latch, the multiple response resolver, the general purpose logic block and a supplies one unit. The interface register logic block provides input/output data registers, mask register, command register, and control/status register. The general control block generates control signals to the CAM system in response to bus signals. The match operation for the CAM array can be performed on all words in a single operation. A set of CAM instructions is used to control CAM operations including data movement, shifting, read/write, and match.