首页>
外国专利>
Numeric processor including a multiply-add circuit for computing a succession of product sums using redundant values without conversion to nonredundant format
Numeric processor including a multiply-add circuit for computing a succession of product sums using redundant values without conversion to nonredundant format
展开▼
机译:包括用于通过使用冗余值计算连续乘积和而不转换为非冗余格式的乘积电路的数值处理器
展开▼
页面导航
摘要
著录项
相似文献
摘要
A numeric processor includes a multiply-add circuit with redundant value interface circuitry for performing mathematical function computations as a succession of product sums using redundant binary format values (such as signed digit) as the multiplicand and/or the addend inputs to the multiply-add circuit. The redundant value interface circuitry (i) extracts a predetermined number of bits from a redundant product sum to form a redundant truncated product sum, and (ii) couples the redundant truncated product sum to either, or both, multiplicand and addend inputs. In this manner, successive redundant product sums are calculated using without conversion to nonredundant binary format. In a preferred embodiment, the numeric processor includes a single multiply- add circuit, with redundant truncated product sum values being fed back to the multiplicand and/or addend inputs.
展开▼