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VLSI circuit structure for implementing JPEG image compression standard
VLSI circuit structure for implementing JPEG image compression standard
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机译:实现JPEG图像压缩标准的VLSI电路结构
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摘要
A fully pipelined VLSI circuit structure for implementing the JPEG baseline image compression standard. The circuit structure exploits the principles of pipelining and parallelism to the maximum extent in order to obtain high speed and throughput. The entire is designed to be implemented on a single VLSI chip to yield a clock rate of about 100 MHz which would allow an input rate of 30 frames per second for 1024× 1024 color images.
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