Electronic equipment having display device in which a shared memory is accessed by both the system and display controllers via a data bus

摘要

A piece of electronic equipment having a display device, the display control is allowed to read out the display data stored in the data storing means when detecting that the central processing unit (CPU) sets the data bus to a high-impedance state. Therefore, the CPU and the display control are inhibited from accessing the data storage at the same time, so that there is no case where erroneous data are read out from or written into or the display is disturbed. Accordingly, the operation data and the display data can be stored into a one-chip data storage. Further, since the data bus is periodically set to the high-impedance by the CPU, the CPU can accurately count a predetermined time with the soft timer program.