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MEMORY SUPERVISORY AND CONTROLLING SYSTEM FOR MAIN SIGNAL BY ODD/EVEN NUMBER ALTERNATE CHECK

机译:奇/偶数交替校验的主信号存储监控系统

摘要

PROBLEM TO BE SOLVED: To improve the supervisory ability of a main signal memory by counting addresses at the time of write and read, measuring the data storage amount of a main signal memory part and switching the odd/even number of a party bit, when a prescribed value is reached. ;SOLUTION: When a write address is generated from a write address counter 4, a state management part 6 adds one to the data storage amount. A change point detection part 8 monitors the data storage amount of the state management part 6, and when the prescribed value is reached, sends odd/even number switching signals to a parity generation part 1 and switches the off number/even number of a parity. At the same tome, the prescribed value is loaded to a down counter 7. In the other hand, when a read address is generated from a read address counter 5, the data storage amount of the state management part 6 and the down counter 7 and the counter value of the down counter 7 are decreased by one. Here, when the counter value of the down counter 7 turns from '1' to '0', the change point detection part 8 sends the odd/even number switching signals to the parity generation part 1 and switches the odd number/even number of the parity.;COPYRIGHT: (C)1998,JPO
机译:解决的问题:通过在写入和读取时对地址进行计数,测量主信号存储部分的数据存储量并在切换时改变偶数位的奇/偶数来提高主信号存储器的监视能力。达到规定值。 ;解决方案:当从写地址计数器4生成写地址时,状态管理部分6将一个数据存储量加1。变化点检测部分8监视状态管理部分6的数据存储量,并且当达到规定值时,将奇/偶数切换信号发送到奇偶校验生成部分1,并且关闭奇偶校验的断开/偶数数目。 。同时,将规定值加载到递减计数器7。另一方面,当从读地址计数器5生成读地址时,状态管理部6和递减计数器7的数据存储量和递减计数器7的计数器值减少1。在此,当减数计数器7的计数器值从“ 1”变为“ 0”时,变化点检测部8将奇/偶数切换信号发送给奇偶校验生成部1,并切换奇偶/偶数切换部7。平价;版权:(C)1998,日本特许厅

著录项

  • 公开/公告号JPH10135961A

    专利类型

  • 公开/公告日1998-05-22

    原文格式PDF

  • 申请/专利权人 NEC CORP;

    申请/专利号JP19960284250

  • 发明设计人 NAGAMOTO MAMORU;

    申请日1996-10-25

  • 分类号H04L12/28;G06F11/10;H04J3/14;H04L1/00;

  • 国家 JP

  • 入库时间 2022-08-22 03:07:11

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