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MEMORY SUPERVISORY AND CONTROLLING SYSTEM FOR MAIN SIGNAL BY ODD/EVEN NUMBER ALTERNATE CHECK
MEMORY SUPERVISORY AND CONTROLLING SYSTEM FOR MAIN SIGNAL BY ODD/EVEN NUMBER ALTERNATE CHECK
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机译:奇/偶数交替校验的主信号存储监控系统
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摘要
PROBLEM TO BE SOLVED: To improve the supervisory ability of a main signal memory by counting addresses at the time of write and read, measuring the data storage amount of a main signal memory part and switching the odd/even number of a party bit, when a prescribed value is reached. ;SOLUTION: When a write address is generated from a write address counter 4, a state management part 6 adds one to the data storage amount. A change point detection part 8 monitors the data storage amount of the state management part 6, and when the prescribed value is reached, sends odd/even number switching signals to a parity generation part 1 and switches the off number/even number of a parity. At the same tome, the prescribed value is loaded to a down counter 7. In the other hand, when a read address is generated from a read address counter 5, the data storage amount of the state management part 6 and the down counter 7 and the counter value of the down counter 7 are decreased by one. Here, when the counter value of the down counter 7 turns from '1' to '0', the change point detection part 8 sends the odd/even number switching signals to the parity generation part 1 and switches the odd number/even number of the parity.;COPYRIGHT: (C)1998,JPO
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