首页> 外国专利> SHIFT REGISTER SERVING BOTH LATCH MODE AND COUNTER MODE AND FLASH MEMORY UTILIZING THE SHIFT REGISTER

SHIFT REGISTER SERVING BOTH LATCH MODE AND COUNTER MODE AND FLASH MEMORY UTILIZING THE SHIFT REGISTER

机译:移位寄存器同时使用锁存器和计数器模式以及闪存,

摘要

PROBLEM TO BE SOLVED: To reduce the count of internal circuits and make a memory highly integrated by letting a shift register circuit carry out both a latch operation and a counter operation. ;SOLUTION: A latch part of a front stage consisting of a NAND circuit 1, an inverter circuit 2 and a switch S3, and a latch part of a rear stage consisting similarly of a NAND circuit 3, an inverter circuit 4 and a switch S5 are connected with each other via switches S2 and S4 in a shift register circuit SF1. Switches S1 and S6 are controlled to be opposite phases by a switch signal command. When the circuit functions as a latch circuit, the switch S1 is turned ON and the switch S6 is turned OFF, thereby simply latching an input INA. On the other hand, when the circuit works as a counter circuit, the switch S1 is turned OFF and the switch S6 is turned ON, thereby constituting a feedback loop and carrying out a count-up operation by a clock signal CLK and an inverted clock signal CLKB.;COPYRIGHT: (C)1998,JPO
机译:要解决的问题:通过让移位寄存器电路执行锁存操作和计数器操作,减少内部电路的数量并使存储器高度集成。 ;解决方案:由NAND电路1,反相器电路2和开关S3组成的前级锁存器部分,以及由NAND电路3,反相器电路4和开关S5类似地组成的后级锁存器部分通过移位寄存器电路SF1中的开关S2和S4彼此连接。通过开关信号命令将开关S1和S6控制为反相。当该电路用作锁存电路时,开关S1被接通并且开关S6被关断,从而简单地锁存输入INA。另一方面,当该电路用作计数器电路时,将开关S1断开并且将开关S6接通,从而构成反馈环路,并通过时钟信号CLK和反相时钟进行递增计数操作。信号CLKB .;版权:(C)1998,JPO

著录项

  • 公开/公告号JPH1064293A

    专利类型

  • 公开/公告日1998-03-06

    原文格式PDF

  • 申请/专利权人 FUJITSU LTD;

    申请/专利号JP19960222619

  • 发明设计人 YANO MASARU;

    申请日1996-08-23

  • 分类号G11C19/00;G11C16/06;H03K21/00;

  • 国家 JP

  • 入库时间 2022-08-22 03:02:46

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号