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Bus transfer response manner

机译:公交换乘方式

摘要

PURPOSE:To simplify a bus interface control circuit and to avoid a delay of a reply cycle time by defining a state of a bus of a status code signal to be 'no answer' when each receiver gives no reply. CONSTITUTION:ID information received by a receiver side bus interface control circuit (BIC) 4 is set to an ID register 8 and its output 8-2 and an output 7-2 of an ID register 7 specific to a receiver are compared by a comparator circuit 9. When the result of comparison is dissident, a driver 17 becomes a high impedance state and the content of an ST register 12 is not outputted to a status code bus 1-3. When the bus 1-3 is not driven from any receiver side BIC 4, the content of the register 13 is referenced from other circuit section of the BIC 4 via a receiver 18 and a status code of 'no answer' is detected, Thus, no bus cycle delay up to the reception of a status code is caused and the bus control circuit of each receiver is formed with the same operation logic and simplified.
机译:目的:通过定义状态码信号的总线状态为“无应答”,以简化总线接口控制电路并避免应答周期时间的延迟,当每个接收器都不应答时。组成:接收器侧总线接口控制电路(BIC)4接收到的ID信息被设置到ID寄存器8,其输出8-2和特定于接收器的ID寄存器7的输出7-2由比较器进行比较当比较结果不同时,驱动器17变为高阻抗状态,ST寄存器12的内容不输出至状态代码总线1-3。当未从任何接收器侧BIC 4驱动总线1-3时,通过接收器18从BIC 4的其他电路部分引用寄存器13的内容,并检测到状态代码“无应答”,因此,不会引起直到接收状态码的总线周期延迟,并且每个接收器的总线控制电路由相同的操作逻辑构成并简化了。

著录项

  • 公开/公告号JP2764452B2

    专利类型

  • 公开/公告日1998-06-11

    原文格式PDF

  • 申请/专利权人 NIPPON DENSHIN DENWA KK;

    申请/专利号JP19900018436

  • 发明设计人 KOMACHA TADAYOSHI;OKADA KATSUYUKI;

    申请日1990-01-29

  • 分类号H04L12/40;G06F13/42;H04L5/22;

  • 国家 JP

  • 入库时间 2022-08-22 03:02:13

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