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Sign method of applying dual-processor configuration DSP

机译:应用双处理器配置DSP的签名方法

摘要

PURPOSE:To attain a high speed operation without stopping one processor completely with the same program by multiplying a result that input data (x) represented in the complement form of 2 of (n) bits is (n-1)-bit-logical-shifted in an LSB direction and that a positive maximum value is added to the shifted result and the operated result of a function f(1x1) together. CONSTITUTION:It is necessary that f(1x1) and -f(1x1) are outputted based on the positive/negative of data so that an output (y) may become point symme try to 0 when a parameter (x) is positive and negative. Then, it is constituted so as to give a code by mutiplying a result that the data (x) inputted in the complement form of n-bit 2 is (n-1)-bit-logical-shifter and that a positive maxi mum value is added to the shifted result and with the operated result of the function f(1x1) together. Thus, a same program can be executed and code giving to the f(1x1) can be executed by both processors without stopping the one proces sor and a high speed operation is attained.
机译:目的:为了获得高速运行而不会用相同的程序完全停止一个处理器,通过乘以一个结果,即以(n)位2的补码形式表示的输入数据(x)是(n-1)-bit-logic-沿LSB方向移位,并且将正最大值加到移位结果和函数f(1x1)的运算结果上。组成:有必要基于数据的正/负输出f(1x1)和-f(1x1),以便当参数(x)为正和负时,输出(y)可能变为点对称尝试为0。 。然后,构成为使得通过以n位2的补码形式输入的数据(x)为(n-1)位逻辑移位器并且最大正值为正,从而给出代码来进行编码。被加到移位后的结果上,并与函数f(1x1)的运算结果加在一起。因此,可以在不停止一个处理器的情况下由两个处理器执行相同的程序,并且可以对两个处理器执行赋予f(1x1)的代码,从而实现高速操作。

著录项

  • 公开/公告号JP2756175B2

    专利类型

  • 公开/公告日1998-05-25

    原文格式PDF

  • 申请/专利权人 ARUPAIN KK;

    申请/专利号JP19900213477

  • 发明设计人 MATSUYAMA MINORU;

    申请日1990-08-10

  • 分类号G06F17/10;

  • 国家 JP

  • 入库时间 2022-08-22 03:01:13

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