High speed PWM without linearity compromise at extreme duty cycles

摘要

A circuit for reducing the amount of instability in a pulse width modualtion circuit by providing a minimum amount of overdrive after the crossover point between a ramp and a voltage threshold level (V₁,VN), and a constant amount of discharge time (Control 1) between the end on one ramp and the beginning of the next. Also, a feedback loop (CH,Ch,l₁,l₂) is provided to increase or decrease the slope to compensate for a decreasing or increasing amount of time between clock pulses, to maintain the duty cycle of the output when the clock frequency varies.