Integrated circuit layout design method and semiconductor structure using functional cell formed by fixed base cell and configurable interconnection network

摘要

A group of functional cells 40 generated from one or more fixed base cell 20 implementations are used to design a layout for a minimal portion of an integrated circuit. Each basic cell implementation may be arranged in a transistor pattern substantially identical to the transistor pattern of each of the other basic cell implementations or a plurality of unconnected transistors Q1 through Q10 arranged in a mirror of each of the other basic cell implementations . A transistor of the characteristic polarity type of each basic cell implementation typically has two or more different current transfer capabilities. Each functional cell has an interconnect network (42-44) for electrically interconnecting the transistors of the functional cell to perform certain electronic functions. The functional cell typically forms a cell library in which a functional cell is selected to generate a layout. The layout technique of the present invention is particularly applicable to the layout of the data path circuit 90 of the integrated circuit.