A synchronous DRAM having active internal supply voltage generating means controlled by the burst mode;

摘要

The present invention relates to a synchronous DRAM having active internal supply voltage generating means controlled by a burst mode. A control signal generating means for generating a first control signal indicating an active state, a second control signal activated until a burst operation ends after a read command is issued, and a third control signal activated until a burst operation is completed, A burst signal generating means for generating a fourth control signal informing of the burst operation with the second and third control signals as inputs, and an internal power supply voltage controlled by the first control signal and the fourth control signal, And an active internal power supply voltage generating means for generating an active internal power supply voltage. Therefore, in the synchronous DRAM having the active internal supply voltage generating means controlled by the burst mode according to the present invention, the active internal supply voltage can be sufficiently supplied to each circuit even when operating in the burst mode.