Frequency synthesiser using fractional frequency synthesis

摘要

The frequency synthesiser includes a phase-regulated oscillator (1), coupled to a phase detector (2) via a frequency divider (3) with a whole number division ratio (N). An output frequency (fi) is provided which is compared in phase with a reference frequency (fr). The control line between the output of the phase detector and the control input of the oscillator contain a loop filter (4). A fractional frequency division ratio is selected by an adjustment unit (5) coupled to a control circuit (7), with periodic switching of the division ratio for minimising phase noise in the oscillator output signal (fo). The control circuit output signal is obtained by adding a whole number component (P) of the division ratio to a supplementary component provided by an integrator chain divided into several sections, for simulating a fractional division ratio.