Reconfiguration procedure for programmable blocks at runtime

摘要

The invention relates to a method for reconfiguration during the running time of FPGA, in which there is a loading logic or several loading logics which react to signals of any kind and recognize and can process special loading logic commands within a configuration programme consisting of data and commands, and, on the basis of the source of an event, can compute an entry in a branch table. For this, there are one or more branch tables for locating the address of the configuration data to be loaded after computing. One or more configuration memory areas exist, in which one or more configuration programmes are loaded; and there are one or more FIFO memory areas into which configuration data is copied which could not be sent to the element or elements to be configured. When an event occurs, an address is computed in a branch table, based on the source of the event. FIFO memory area is provided and run through before each reloading, and, if the cell can not be reloaded, the configuration data is copied into it nearer the beginning; if the cell can be reloaded, the configuration data is transferred to the cell. The computed branch table entry is read-out, and the configuration data which is stored at the read-out address is loaded into the cell, or, if the cell cannot be reprogrammed, it is copied into the FIFO memory area.