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Cache - memory with the possibility of erroneous handle in the case at the same time to update and a decision on the next address to meet

机译:高速缓存-内存可能在错误的情况下同时更新并决定下一个要满足的地址

摘要

In a cache memory simultaneously conducting updating for a mishit and a decision on a mishit for the subsequent address, a write flag (15) generated by a control unit (18) is written in a valid flag field (9a). Based on this method, during an access to an external memory at an occurrence of a mishit, a tag field (6a) and the valid flag field are simultaneously updated. When updating a data field (8), a read operation is achieved on the tag and valid flag fields to decide occurrence of a mishit. Thus, an external memory access for a mishit at a next address can be executed at an earlier point of time. Moreover, by the provision of a data latch (21) disposed for an output from the data field, and by reading data at a next address and keeping it in the data latch (21) during a memory read cycle (C1, C3), succeeding hit data can be outputted immediately after a mishit processing is completed. Furthermore, also in a cache memory having a plurality of tag fields (6a, 6b) and a plurality of valid flag fields (9a, 9b), the updating for a mishit and the decision on a mishit for a next address can be attained at the same time.
机译:在同时进行误命中的更新和对随后地址的误命中的判定的高速缓冲存储器中,由控制单元(18)产生的写标志(15)被写入有效标志字段(9a)中。基于该方法,在发生误命中访问外部存储器的过程中,标签字段(6a)和有效标志字段被同时更新。当更新数据字段(8)时,将在标签和有效标志字段上执行读取操作,以判断是否发生误击。因此,可以在较早的时间执行对下一个地址的错误命中的外部存储器访问。此外,通过提供设置用于从数据字段输出的数据锁存器(21),并且在存储器读取周期(C1,C3)期间通过读取下一个地址的数据并将其保持在数据锁存器(21)中,误击处理完成后,可以立即输出后续的命中数据。此外,在具有多个标签字段(6a,6b)和多个有效标志字段(9a,9b)的高速缓冲存储器中,也可以通过以下步骤获得误命中的更新和对下一地址的误命中的判定。同一时间。

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