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Testable ram - architecture in a microprocessor with an embedded cache - memory
Testable ram - architecture in a microprocessor with an embedded cache - memory
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机译:可测试的RAM-具有嵌入式缓存的微处理器中的体系结构-内存
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摘要
A microprocessor (100) with embedded cache memory (204) is disclosed. In a "test mode" of operation, caches (204) are accessed directly from the memory interface signals. Direct writing and reading to/from the instruction and data caches (204) allows the testing of the functionality of the cache memory arrays (204). External memory interface is granted to an external master via a bus arbitration mechanism so that the test mode operation can be utilized. IMAGE
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