demodulator and demodulation method for msk - win, digital signals

摘要

Disclosed is a demodulation circuit for demodulating a modulated signal obtained by minimum shift keying. The demodulation circuit includes two synchronous detection circuits (11, 12) for detecting the modulated signal synchronously with two signals having the phases different from each other by 90 DEG , respectively, a circuit (17) for discriminating the amplitude of the output signal of one of the synchronous detection circuits (11) to convert the output signal into a rectangular wave having two logical levels, and a circuit (24) for sampling the rectangular wave signal in synchronization with a clock signal having a frequency corresponding to one-bit duration of the digital data. Both of two signals having the phases different by 90 DEG from each other, all of which are necessary for the synchronous detection, and the clock signal are generated based on a signal (Vt ( theta )) obtained by multiplying the output signal of the one of the synchronous detection circuits and the output signal of the other of the synchronous detection circuits. IMAGE