Decoding unit, which is constructed as emitter-coupled logic circuit with a high switching speed, and low power consumption

摘要

PURPOSE:To attain a high speed operation without increasing power consumption with respect to an increase in the load capacitance by providing transistors(TRs) whose emitters are connected in common and a resistor or the like to optimize a switching timing of the TRs to each output of a decode circuit. CONSTITUTION:An output level decreasing current source ICS is connected to an emitter common connecting point of TRs QS1-QSn whose bases are connected to collectors via resistors RS1, RS2... and whose emitters are connected to each output of a decode circuit of an ECL logic circuit using a high potential as a selected level. The current switching timing is optimized by the resistors RS1-RSn connected to bases of the TRsQS1-QSn of diode connection subtracting a current selectively from the high potential output and the compatibility between high speed response and low power consumption is attained to the increase in load capacitors C1-Cn.