digital schiebungs and summierungssignalprozessor

摘要

A shift and add digital image processor (1) includes two sections (3) and (5), each including a latch (10, 22) for latching an input signal, an adder (18, 28) for summing two channels output from the latch with programmable delay (14, 26) therebetween, and a bit-shifting scaler (20, 30) for generating "powers of two" functions from the output of the adder. By selecting the input to the second section (5) either from the output of the first latch (10) or from image pixels delayed by at least one line with respect to the pixels input to the first section (3), the processor may be set up to perform either one- or two-dimensional filter functions.