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Multiplier circuit in a galois field and applications of such a circuit in a processing device and error corrector
Multiplier circuit in a galois field and applications of such a circuit in a processing device and error corrector
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机译:伽罗瓦场中的乘法器电路及其在处理设备和纠错器中的应用
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摘要
Multiplications on a finite field of cardinal 2m may be achieved by means of a multiplier circuit including j shift registers (R0, ..., Rj-1) into which dual-base co-ordinates of one operand are initially loaded, j being an integer greater than 1 divisor of m. The other operand is expressed in standard base. The shift registers are linked to combinatorial logics arranged to deliver the dual-base co-ordinates of the product of the two operands in m/j clock cycles, with j co-ordinates being delivered in each cycle. Multiplication execution rates may thus be increased relative to previously known dual-base multipliers that required at least m clock cycles per operation. The multiplier circuit is particularly useful in BCH decoders.
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