Three inverter gate CMOS ring oscillator for integrated circuit clock signal

摘要

The ring oscillator includes a first inverting logic gate (1), a threshold amplifier (2) and a second logic gate inverter (3). There is a delay circuit (R, C), including a series resistance and a parallel capacitor, located at the input (E) of the threshold amplifier. This includes an inverter stage (2a) with an upper branch of P channel MOS transistors, and a lower branch with N type MOS transistors, and an output inverter stage at the junction of the branches. Upper and lower biassing transistors (T5,T6) allows the ratio of the fall threshold voltage to the supply voltage to rise, and the latter allows the ratio of the rise threshold voltage to the supply voltage to fall when the supply voltage decreases. The gates to these transistors are controlled by biasing circuits (T7, T8, T9, T10) whose gates are controlled by the output (S) of the inverter stage and the output (OSC) of the second inverter gate.