Method and apparatus for quick and reliable design modification on silicon

摘要

In order to reduce product's time to market, a designer has to plan for debugging silicon before the first tape out. Having the proper type of spare gates at the desirable location will limit the number of new masks to three if not just one. Moreover, when these spare gates are easy to locate and are in the proper format, a FIB system can be used to debug the silicon and test the new fixes in real system environment before the next tape out. Thus, the spare gate strategy can limit the iteration of mask changes to just one, and this will speed up the time to market and bring higher profit from the product.