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Single chip controller-memory device with interbank cell replacement capability and a memory architecture and methods suitble for implementing the same
Single chip controller-memory device with interbank cell replacement capability and a memory architecture and methods suitble for implementing the same
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机译:具有库间单元替换能力的单芯片控制器存储器设备以及适用于实现该控制器的存储器架构和方法
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摘要
A memory subsystem 300 including processing circuitry 103 and first and second banks of memory 200/201. Each bank 200/201 includes a predetermined number of primary memory cells 200 and a predetermined number of redundant memory cells 205. An address bus 202 allows processing circuitry 103 to address at least one of the primary cells 200. The redundancy bus 301 allows processing circuitry 103 to address at least one of the redundancy cells 205.
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