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Instruction cache system for implementing programs having non- sequential instructions and method of implementing same

机译:用于实现具有非顺序指令的程序的指令缓存系统及其实现方法

摘要

A system for increasing the speed and efficiency of instruction execution by a computer processing system. An instruction cache is provided to receive a minor number of stored instructions for execution by the computer processing system. The instructions are prefetched and returned in cache based upon an analysis of instructions which are in the cache pending execution. Target instructions of branch instructions may be prefetched as a result of the analysis of a branch instruction pending in the cache. Other instructions may be retained in cache when they are tagged as being likely to be reused.
机译:一种用于提高计算机处理系统的指令执行速度和效率的系统。提供指令高速缓存以接收少量存储的指令以供计算机处理系统执行。根据对高速缓存中等待执行的指令的分析,预取指令并在高速缓存中返回指令。分支指令的目标指令可以作为缓存中待处理的分支指令的分析结果而被预取。当其他指令被标记为可能被重用时,它们可以保留在缓存中。

著录项

  • 公开/公告号US5701435A

    专利类型

  • 公开/公告日1997-12-23

    原文格式PDF

  • 申请/专利权人 PHILIPS ELECTRONICS NORTH AMERICA CORPORATION;

    申请/专利号US19930063845

  • 发明设计人 CHI-HUNG CHI;

    申请日1993-05-19

  • 分类号G06F12/12;

  • 国家 US

  • 入库时间 2022-08-22 02:40:37

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