Automatic instruction string generation method and device for verifying processor operation model and logic

摘要

First, an initial operation model M.sub.0 of a pipeline is configured according to the pipeline configuration of a processor and the specification information about an instruction executed by the processor. Then, the number of the states of the initial operation model M.sub.0 is minimized to configure an operation model M. Based on the operation model M and a test state set H, listed are test instruction strings for the process in which the state of the operation model M indicates a transition from a predetermined input state to any of the test states contained in the test state set H without an occurrence of a conflict in the operation model M. A next time state, reached after the state of the operation model M has reached the test state of the test instruction string, is calculated and the next time state is input as a new input state to a test instruction string listing unit.